RF receivers in RF communication systems are well known in the art. RF mixers are fundamental building blocks in RF receivers. In a typical RF receiver architecture, a Low Noise Amplifier (LNA) amplifies a weak signal received at an antenna, and passes the amplified received signal to an RF mixer for down-conversion. The RF mixer down-converts the received signal from a carrier frequency to an intermediate frequency by mixing it with a signal from a local oscillator. The intermediate frequency signal may then be filtered and processed to convert it to a baseband frequency.
A Zero Intermediate Frequency (ZIF) receiver—also known in the art as a homodyne or “direct conversion” receiver—converts an input RF signal directly to baseband. ZIF receivers are more easily integrated into integrated circuits, as the need for pass-band filters is eliminated, and the space requirement and complexity are reduced.
Mixers in practice may be designed as passive or active. Active mixers can provide gain while down converting the RF signal, but are generally less linear and have higher noise figures—particularly the flicker noise contribution, which is harmful for narrow band RF applications such as GSM.
RF communication systems usually demand a duplex operation mode in a transceiver, wherein the receiver and transmitter work simultaneously. Because the transmitter emits signals at high power levels, the receiver suffers from interference. As a result, very good linearity is required for both the LNA and the mixer. For a ZIF or direct conversion receiver, protecting the receiver from interference created by transmitter is very important. In particular, the second order intermodulation product must be minimized. The measure of this is known as the second order input intercept point (IIP2).
In order to reach better IIP2, RF signals can be processed differentially. Differential RF receivers use a symmetric topology, in which nonlinearity caused by device parameters is cancelled. For this purpose, using a Balun to do single-end to differential conversion is beneficial. However, for quadrature mixer operation, a two-phase clock scheme is not possible unless isolation is provided, since the two output loads will interact, resulting in lower conversion gain, lower linearity, and IQ leakage. A known mixer architecture that solves this problem uses a four-phase clock scheme. This isolates four conducting periods, i.e., interleaving I and Q, but does not short-circuit the two loads.
It is known to use feedback to suppress the second order intermodulation component, and effectively increase the IIP2. An article by Brandolini, et al., titled “A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS,” published in the Journal of Solid-State Circuits, June 2007, incorporated herein by reference in its entirety, describes one means to do so. The output common-mode level is detected and compared to the desired DC output common-mode level. The discrepancy is then fed back as an error signal to voltage controlled current sources, forming a negative feedback loop. However, the technique used in the article addresses how to make the IIP2 compensation for an active mixer, i.e. a Gilbert topology, where the feedback signal controls the bias currents. Since the feedback loop is placed inside the mixer core, there is no problem having two IIP2-compensated mixers work in parallel, e.g. in an IQ-architecture.
However, when using two passive mixers in an IQ-architecture fed by a differential balun, the error signals from the mixers must be fed back to a joint input source, i.e. if the feedback signal from each mixer is not separated in the time domain, the feedback path will be corrupted. For example, in FIG. 1, CT,Q and CT,I will create distortion if connected together to the center tap CT of the input signal source.